0

5

10

15

ICC

IDD

G016

44.1(1)

96(3)

48(2)

(1) System Clock = 384 fS

(2) System Clock = 512 fS

(3) System Clock = 256 fS

fSAMPLE Condition − kHz

−100

−90

−80

−70

−60

−50

−40

−30

−20

−10

0

−100 −90 −80 −70 −60 −50 −40 −30 −20 −10

0

Signal Level − dB

G015

PCM1808-Q1

SLES265A – MARCH 2011 – REVISED AUGUST 2012

www.ti.com

TYPICAL PERFORMANCE CURVES (Continued)

All specifications at TA = 25°C, VCC = 5 V, VDD = 3.3 V, master mode, fS = 48 kHz, system clock = 512 fS, 24-bit data, unless

otherwise noted.

OUTPUT SPECTRUM (Continued)

THD + N

vs

SIGNAL LEVEL

Figure 15.

SUPPLY CURRENT

SUPPLY CURRENT

vs

fSAMPLE CONDITION

Figure 16.

10

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