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PCM1808 데이터시트(PDF) 13 Page - Texas Instruments

부품명 PCM1808
상세설명  SINGLE-ENDED, ANALOG-INPUT 24-BIT, 96-kHz STEREO A/D CONVERTER
PDF  29 Pages
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제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

PCM1808 데이터시트(HTML) 13 Page - Texas Instruments

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Clock-Halt Reset
SCKI
T0081-01
48/fin or 48/fS
Fade-In Start
Fade-In Complete
Internal
Reset
Operation
Operation
DOUT
Normal Data
Normal Data
DOUT
(Contents)
Normal Data
SCKI Halt
SCKI Resume
Fixed to Low or High
t(CKR)
Reset: t(RST)
Reset Release: t(REL)
BPZ
Zero Data
PCM1808-Q1
www.ti.com
SLES265A – MARCH 2011 – REVISED AUGUST 2012
CLOCK-HALT POWER-DOWN AND RESET FUNCTION
The PCM1808-Q1 has a power-down and reset function, which is triggered by halting SCKI (pin 6) in both
master and slave modes. The function is available anytime after power on. Reset and power down are performed
automatically 4
μs (minimum) after SCKI is halted. While the clock-halt reset is asserted, the PCM1808-Q1 stays
in the reset and power-down mode, and DOUT (pin 9) is forced to zero. SCKI must be supplied to release the
reset and power-down mode. The digital output is valid after the reset state is released and the time of 1024
SCKI + 8960/fS has elapsed. Because the fade-in operation is performed, it takes additional time of 48/fin or 48/fS
until the level corresponding to the analog input signal is obtained. Figure 20 illustrates the clock-halt reset
timing.
To avoid ADC performance degradation, BCK (pin 8) and LRCK (pin 7) are required to synchronize with SCKI
within 4480/fS after SCKI is resumed. If it takes more than 4480/fS for BCK and LRCK to synchronize with SCKI,
SCKI should be masked until the synchronization is achieved again, taking care of glitch and jitter. See the
typical circuit connection diagram, Figure 26.
To avoid ADC performance degradation, the clock-halt reset also should be asserted when system clock SCKIor
the audio interface clocks BCK and LRCK (sampling rate fS) are changed on the fly.
SYMBOL
PARAMETER
MIN
MAX
UNIT
t(CKR)
Delay time from SCKI halt to internal reset
4
μs
t(RST)
Delay time from SCKI resume to reset release
1024 SCKI
μs
t(REL)
Delay time from reset release to DOUT output
8960/fS
μs
Figure 20. Clock-Halt Power-Down and Reset Timing
Copyright © 2011–2012, Texas Instruments Incorporated
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