PIC12LF1552 datasheet(21/356 Pages) MICROCHIP

21 / 356 page

 2015-2016 Microchip Technology Inc.

Preliminary

DS40001817B-page 21

PIC16LF1566/1567

2.1

Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 7.5 “Automatic Context Saving”,

for more information.

2.2

16-Level Stack with Overflow and

Underflow

These devices have a hardware stack memory 15 bits

wide and 16 words deep. A Stack Overflow or

Underflow will set the appropriate bit (STKOVF or

STKUNF) in the PCON register, and if enabled, will

cause a software Reset. See section Section 3.4

“Stack”

for more details.

2.3

File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one Data Pointer for all memory. When an

FSR points to program memory, there is one additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can now

also be addressed linearly, providing the ability to

access contiguous data larger than 80 bytes. There are

also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing”

for more details.

2.4

Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 24.0 “Instruction Set Summary”

for more

details.

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