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ST7262 데이터시트(PDF) 113 Page - STMicroelectronics

부품명 ST7262
상세설명  LOW SPEED USB 8-BIT MCU WITH 3 ENDPOINTS, FLASH OR ROM MEMORY, LVD, WDG, 10-BIT ADC, 2 TIMERS, SCI, SPI
PDF  139 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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ST7262 데이터시트(HTML) 113 Page - STMicroelectronics

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I/O PORT PIN CHARACTERISTICS (Cont’d)
Figure 71. Typical VDD-VOH vs. VDD (high sink port)
12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V, not tested in production.
2. Data guaranteed by design.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2 and the sum of IIO (I/
O ports and control pins) must not exceed IVSS.
5. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-
scribed in Figure 72). This data is based on characterization results, not tested in production.
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
3.5
4
4.5
5
5.5
6
Vdd (V)
0
0.05
0.1
0.15
0.2
0.25
3.5
4
4.5
5
5.5
6
Vdd (V)
Symbol
Parameter
Conditions
Min
Typ 1)
Max
Unit
VIH
Input High Level Voltage
0.7xVDD
VDD
V
VIL
Input Low Voltage
VSS
0.3xVDD
V
Vhys
Schmitt trigger voltage hysteresis 3)
400
mV
VOL
Output low level voltage 4)
(see Figure 73, Figure 74)
VDD=5V
IIO=5mA
1 2)
V
IIO=2mA
0.4 2)
RON
Weak pull-up equivalent resistor 5)
VIN=VSS
60
k
tw(RSTL)out Generated reset pulse duration
External pin or
internal reset sources
6
30
1/fSFOSC
µs
th(RSTL)in External reset pulse hold time
6)
10
µs



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