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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7262 데이터시트(PDF) 12 Page - STMicroelectronics |
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ST7262 데이터시트(HTML) 12 Page - STMicroelectronics |
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12 / 139 page  ST7262 12/139 Table 2. Hardware Register Map Address Block Register Label Register Name Reset Status Remarks 0000h 0001h Port A PADR PADDR Port A Data Register Port A Data Direction Register 00h1) 00h R/W2) R/W2) 0002h 0003h Port B PBDR PBDDR Port B Data Register Port B Data Direction Register 00h1) 00h R/W2) R/W2) 0004h 0005h Port C PCDR PCDDR Port C Data Register Port C Data Direction Register 00h1) 00h R/W2) R/W2) 0006h 0007h Port D PDDR PDDDR Port D Data Register Port D Data Direction Register 00h1) 00h R/W2) R/W2) 0008h ITRFRE1 Interrupt Register 1 00h R/W 0009h MISC Miscellaneous Register 00h R/W 000Ah 000Bh 000Ch ADC ADCDRMSB ADCDRLSB ADCCSR ADC Data Register (bit 9:2) ADC Data Register (bit 1:0) ADC Control Status Register 00h 00h 00h Read Only Read Only R/W 000Dh WDG WDGCR Watchdog Control Register 7Fh R/W 000Eh 0010h Reserved Area (3 Bytes) 0011h 0012h 0013h SPI SPIDR SPICR SPICSR SPI Data I/O Register SPI Control Register SPI Control Status Register xxh 0xh 00h R/W R/W Read Only 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch PWM ART PWMDCR1 PWMDCR0 PWMCR ARTCSR ARTCAR ARTARR ARTICCSR ARTICR1 ARTICR2 PWM AR Timer Duty Cycle Register 1 PWM AR Timer Duty Cycle Register 0 PWM AR Timer Control Register Auto-Reload Timer Control/Status Register Auto-Reload Timer Counter Access Register Auto-Reload Timer Auto-Reload Register ART Input Capture Control/Status Register ART Input Capture Register 1 ART Input Capture Register 2 00h 00h 00h 00h 00h 00h 00h 00h 00h R/W R/W R/W R/W R/W R/W R/W Read Only Read Only 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h SCI SCIERPR SCIETPR SCISR SCIDR SCIBRR SCICR1 SCICR2 SCI Extended Receive Prescaler register SCI Extended Transmit Prescaler Register Reserved Area SCI Status register SCI Data register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 00h 00h -- C0h xxh 00h x000 0000b 00h R/W R/W Read Only R/W R/W R/W R/W |
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