ST7262 datasheet(47/139 Pages) STMICROELECTRONICS

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ST7262

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PWM AUTO-RELOAD TIMER (Cont’d)

Output compare and Time base interrupt

On overflow, the OVF flag of the ARTCSR register

is set and an overflow interrupt request is generat-

ed if the overflow interrupt enable bit, OIE, in the

ARTCSR register, is set. The OVF flag must be re-

set by the user software. This interrupt can be

used as a time base in the application.

External clock and event detector mode

Using the fEXT external prescaler input clock, the

auto-reload timer can be used as an external clock

event detector. In this mode, the ARTARR register

is used to select the nEVENT number of events to

be counted before setting the OVF flag.

nEVENT = 256 - ARTARR

When entering HALT mode while fEXT is selected,

all the timer control registers are frozen but the

counter continues to increment. If the OIE bit is

set, the next overflow of the counter will generate

an interrupt which wakes up the MCU.

Caution: If HALT mode is used in the application,

prior to executing the HALT instruction, the coun-

ter must be disabled by clearing the TCE bit in the

ARTCSR register to avoid spurious counter incre-

ments.

Figure 35. External Event Detector Example (3 counts)

COUNTER

FDh

FEh

FFh

FDh

OVF

ARTCSR READ

INTERRUPT

ARTARR=FDh

fEXT=fCOUNTER

FEh

FFh

FDh

IF OIE=1

INTERRUPT

IF OIE=1

ARTCSR READ

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