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STM32F205RFT6 데이터시트(PDF) 129 Page - STMicroelectronics |
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STM32F205RFT6 데이터시트(HTML) 129 Page - STMicroelectronics |
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129 / 184 page ![]() DocID15818 Rev 15 129/184 STM32F20xxx Electrical characteristics 183 Figure 55. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ and VREF– inputs are both available on UFBGA176 package. VREF+ is also available on all packages except for LQFP64. When VREF+ and VREF– are not available, they are internally connected to VDDA and VSSA. 6.3.21 DAC electrical characteristics Table 68. DAC characteristics Symbol Parameter Min Typ Max Unit Comments VDDA Analog supply voltage 1.8(1) -3.6 V - VREF+ Reference supply voltage 1.8(1) -3.6 V VREF+ ≤VDDA VSSA Ground 0 - 0 V - RLOAD(2) Resistive load with buffer ON 5- - k Ω - RO(2) Impedance output with buffer OFF -- 15 k Ω When the buffer is OFF, the Minimum resistive load between DAC_OUT and VSS to have a 1% accuracy is 1.5 MΩ CLOAD(2) Capacitive load - - 50 pF Maximum capacitive load at DAC_OUT pin (when the buffer is ON). DAC_OUT min(2) Lower DAC_OUT voltage with buffer ON 0.2 - - V It gives the maximum output excursion of the DAC. It corresponds to 12-bit input code (0x0E0) to (0xF1C) at VREF+ = 3.6 V and (0x1C7) to (0xE38) at VREF+ = 1.8 V DAC_OUT max(2) Higher DAC_OUT voltage with buffer ON -- VDDA – 0.2 V |
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