PIC16F753 datasheet(88/230 Pages) MICROCHIP

88 / 230 page

PIC16F753/HV753

DS40001709C-page 88

 2013-2015 Microchip Technology Inc.

When the phase delay count value is zero, phase

delay is disabled and the phase delay counter output

is true, thereby allowing the event signal to pass

straight through to complementary output driver flop.

11.7.1

CUMULATIVE UNCERTAINTY

It is not possible to create more than one COG_clock of

uncertainty by successive stages. Consider that the

phase delay stage comes after the blanking stage, the

dead-band stage comes after either the blanking or

phase delay stages, and the blanking stage comes

after the dead-band stage. When the preceding stage

is enabled, the output of that stage is necessarily

synchronous with the COG_clock, which removes any

possibility of uncertainty in the succeeding stage.

EQUATION 11-1:

PHASE, DEAD-BAND AND

BLANKING TIME

CALCULATION

EQUATION 11-2:

TIMER UNCERTAINTY

min

Count

max

Count

COG_clock

--------------------------

uncertainty

max

min

–

uncertainty

COG_clock

--------------------------

Also:

Where:

Count

Rising Phase Delay

COGxPHR

Falling Phase Delay

COGxPHF

Rising Dead Band

COGxDBR

Falling Dead Band

COGxDBF

Rising Event Blanking

COGxBKR

Falling Event Blanking

COGxBKF

COG_clock

Given:

Therefore:

Count

10d

COG_Clock

8MHz

uncertainty

COG_clock

--------------------------

8MHz

---------------

125ns

Proof:

min

Count

COG_clock

--------------------------

125ns

10d



1.25

s

max

Count

COG_clock

--------------------------

125ns

10d





1.375

s

Therefore:

uncertainty

max

min

–

1.375

s 1.25s

–

125ns

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