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IP1001-DS-R02 데이터시트(PDF) 20 Page - List of Unclassifed Manufacturers

부품명 IP1001-DS-R02
상세설명  Integrated 10/100/1000 Gigabit Ethernet Transceiver
PDF  48 Pages
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IP1001 LF
Data Sheet
3.3
Serial Management Interface
The serial management interface consisting of two pins, MDC and MDIO, provides access to the MII registers
of IP1001. MDC is a clock input and runs at a maximum rate of 12.5 MHz. MDIO is a bi-directional data pin
that runs synchronously to MDC. The MDIO pin requires a 5.1-k
Ω pull up resistor. To access MII register in
IP1001, MDC should be at least one more cycle than MDIO. That is, a complete command consists of 32 bits
MDIO data and at least 33 MDC clocks.
Frame
format
<Idle><start><op code><PHY address><Registers address><turnaround><data><idle>
Read
Operation
<Idle><01><10><A4A3A2A1A0><R4R3R2R1R0><Z0><b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
Write
Operation
<Idle><01><01><A4A3A2A1A0><R4R3R2R1R0><10><b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1b0><Idle>
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
0
1..1
idle
start
op
code
PHY address =
01h
Reg address =
00h
TA
Register data
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
idle
A
4
A
3
A
2
A
1
A
0
R
4
R
3
R
2
R
1
R
0
write
z
z
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
Z
0
0
0
0
0
1
0
0
0
0
0
1
1
0
idle
start
op
code
PHY address =
01h
Reg address =
00h
TA
Register data
b
1
5
b
1
4
b
1
3
b
1
2
b
1
1
b
1
0
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
idle
A
4
A
3
A
2
A
1
A
0
R
4
R
3
R
2
R
1
R
0
read
z
zz
MDC
MDIO
MDC
MDIO
1..1
1..1
1..1
3.4
LED
IP1001 provides 3 LED pins, LED0~2, and four LED display modes, mode0~3. User can select one of four
LED modes by configuring LED_MODE1 and LED_MODE0. LED_MODE1 and LED_MODE0 are defined in
register 16[15:14]. Pin 55 LED_MODE0 defines the default value of register 16[14].
The functionality of the LED pins is shown in the table below. The driving capability of LED pins can be
programmed by writing MII register 16[13].
LED mode setting
R24
5.1K
LED mode 1
TX_CLK/LED_MODE0
LED mode 0
VDDO
TX_CLK/LED_MODE0
R44
5.1K
Dec. 18, 2007
20/48
Copyright © 2006, IC Plus Corp.
IP1001-DS-R06



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