IP1000A LF
Preliminary Data Sheet
57/75
July 5, 2005
Copyright © 2005, IC Plus Corp.
IP1000A LF-DS-R08
3.2.2.18 NextItemPtr0
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x51
Default Value ................ 0x60
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
NextItemPtr
Next Item Pointer. NextItemPtr indicates the next
capability data structure in the capabilities list.
When NextItemPtr is set to the value 0x00, there
are no further data structures.
R
3.2.2.19 NextItemPtr1
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x61
Default Value ................ 0x00
Access Rule.................. Byte
Width ............................ 8 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
7..0
NextItemPtr
Next Item Pointer. NextItemPtr indicates the next
capability data structure in the capabilities list.
When NextItemPtr is set to the value 0x00, there
are no further data structures.
R
3.2.2.20 PowerMgmtCap
Class............................. PCI Configuration Registers
I/O Base Address ......... PCI device configuration header start
Address Offset .............. 0x52
Default Value ................ 0x7602
Access Rule.................. Word
Width ............................ 16 bits
Bit
BIT Name
BIT Description
Type
HW
Reset
SW
Reset
2..0
Version
Version. Version is set to 0x2, indicating PCI Bus
Power Management Specification Revision 1.1.
R
8..3
Reserved
Reserved for future use. Write as zero, ignore on read.
N/A
9
D1Support
D1 Power State Support. When D1Support is a
logic 1, the IP1000A LF supports the D1 power
state (see section 2.2.5.1).
D1Support is loaded from the ConfigParm field of an
EEPROM during auto initialization of the IP1000A
LF.
R
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