ADC12D040CIVSSLASHNOPB datasheet(4/31 Pages) TI2

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DGND

ADC12D040

SNAS171E – JUNE 2002 – REVISED MARCH 2013

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PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

Non-Inverting analog signal Inputs. With a 2.0V reference the full-

VINA+

scale input signal level is 2.0 VP-P on each pin of the input pair,

VINB+

centered on a common VCM.

Inverting analog signal Input. With a 2.0V reference the full-scale

input signal level is 2.0 VP-P on each pin of the input pair, centered

VINA−

on a common VCM. These (-) input pins may be connected to a

VINB−

common VCM for single-ended operation, but a differential input

signal is required for best performance.

Reference input. This pin should be bypassed to AGND with a 0.1

VREF

µF monolithic capacitor when external reference is used. VREF is

2.0V nominal and should be between 1.0V to 2.4V.

VREF select pin. With a logic low at this pin the internal 2.0V

INT/EXT REF

reference is selected. With a logic high on this pin an external

reference voltage must be applied to VREF input pin 7.

VRPA

VRPB

VRMA

VRMB

These pins are high impedance reference bypass pins only. Connect

a 0.1 µF capacitor from each of these pins to AGND. DO NOT LOAD

these pins.

VRNA

VRNB

DIGITAL I/O

Digital clock input. The range of frequencies for this input is 100 kHz

CLK

to 55 MHz (typical) with guaranteed performance at 40 MHz. The

input is sampled on the rising edge of this input.

OEA and OEB are the output enable pins that, when low, enables

OEA

their respective TRI-STATE data output pins. When either of these

OEB

pins is high, the corresponding outputs are in a high impedance

state.

PD is the Power Down input pin. When high, this input puts the

converter into the power down mode. When this pin is low, the

converter is in the active mode.

Output Format pin. A logic low on this pin causes output data to be

in offset binary format. A logic high on this pin causes the output

data to be in 2’s complement format.

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