ADC12D040

SNAS171E – JUNE 2002 – REVISED MARCH 2013

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Converter Electrical Characteristics (continued)

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA VD +5V, VDR +3.0V, PD

= 0V, INT/EXT = VD, VREF = +2.0V,OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits apply for TJ

= TMIN to TMAX: all other limits TJ = 25°C

(1)(2)

Typical

Limits

Units

Symbol

Parameter

Conditions

(3)

(3)

(Limits)

REFERENCE AND ANALOG INPUT CHARACTERISTICS

(CLK LOW)

8

pF

CIN

VIN Input Capacitance (each pin to GND)

VIN = 2.5 Vdc + 0.7 Vrms

(CLK HIGH)

7

pF

1.0

V (min)

VREF

Input Reference Voltage(5)

2.00

2.4

V (max)

RREF

Reference Input Resistance

100

M

Ω (min)

0

V (min)

VIN

Analog Input Voltage Range

4

V (max)

(5)

Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.4V range. The LM4051CIM3-ADJ (SOT23

package) is recommended for this application.

DC and Logic Electrical Characteristics

Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =

+3.0V, PD = 0V, INT/EXT = VD, VREF = +2.0V,OEA, OEB = 0V, fCLK = 40 MHz, tr = tf = 3 ns, CL = 20 pF/pin. Boldface limits

apply for TJ = TMIN to TMAX: all other limits TJ = 25°C

(1) (2) (3)

Typical

Limits

Units

Symbol

Parameter

Conditions

(4)

(4)

(Limits)

CLK, PD, OE DIGITAL INPUT CHARACTERISTICS

VIN(1)

Logical “1” Input Voltage

VD = 5.25V

2.0

V (min)

VIN(0)

Logical “0” Input Voltage

VD = 4.75V

1.0

V (max)

IIN(1)

Logical “1” Input Current

VIN = 5.0V

10

µA

IIN(0)

Logical “0” Input Current

VIN = 0V

−10

µA

CIN

Digital Input Capacitance

5

pF

(1)

The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided

current is limited, see Note 4 in the Absolute Maximum Ratings table. However, errors in the A/D conversion can occur if the input goes

above VA or below GND by more than 100 mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure

accurate conversions (see Figure 2).

(2)

To guarantee accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.

(3)

With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV.

(4)

Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to AOQL (Average

Outgoing Quality Level).

8

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