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LP5523 데이터시트(PDF) 40 Page - Texas Instruments

부품명 LP5523
상세설명  LP5523 Nine-Channel RGB- and White-LED Driver With Internal Program Memory and Integrated Charge Pump – DSBGA Package
PDF  61 Pages
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제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
Logo TI2 - Texas Instruments

LP5523 데이터시트(HTML) 40 Page - Texas Instruments

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LP5523
SNVS550E – SEPTEMBER 2009 – REVISED JANUARY 2017
www.ti.com
Product Folder Links: LP5523
Submit Documentation Feedback
Copyright © 2009–2017, Texas Instruments Incorporated
(1)
This opcode is used with numerical operands.
(2)
This opcode is used with variables.
7.6.3 Instruction Set
The LP5523 has three independent programmable execution engines. All the program execution engines have
their own program memory block allocated by the user. Note that in order to access program memory the
operation mode needs to be load program, at least for one of the three program execution engines. Program
execution is clocked with a 32.7-kHz clock. This clock can be generated internally or external 32-kHz clock can
be connected to CLK pin. Using external clock enables synchronization of LED timing to the external clock
signal.
Supported instruction set is listed in the following tables:
Table 4. LP5523 LED Driver Instructions
Inst.
Bit
[15]
Bit
[14]
Bit
[13]
Bit
[12]
Bit
[11]
Bit
[10]
Bit [9] Bit [8]
Bit
[7]
Bit [6] Bit [5] Bit [4] Bit [3] Bit [2] Bit [1]
Bit [0]
ramp(1)
0
pre-
scale
step time
sign
number of increments
ramp(2)
1
0
0
0
0
1
0
0
0
0
pre-
scale
sign
step time
no. of
increments
set_pwm(1)
0
1
0
0
0
0
0
0
PWM value
set_pwm(2)
1
0
0
0
0
1
0
0
0
1
1
0
0
0
PWM value
wait
0
pre-
scale
time
0
0
0
0
0
0
0
0
0
Table 5. LP5523 LED Mapping Instructions
Inst.
Bit
[15]
Bit
[14]
Bit
[13]
Bit
[12]
Bit
[11]
Bit
[10]
Bit
[9]
Bit
[8]
Bit
[7]
Bit
[6]
Bit
[5]
Bit [4]
Bit
[3]
Bit [2]
Bit
[1]
Bit [0]
mux_ld_start
1
0
0
1
1
1
1
0
0
SRAM address 0-95
mux_map_start
1
0
0
1
1
1
0
0
0
SRAM address 0-95
mux_ld_end
1
0
0
1
1
1
0
0
1
SRAM address 0 - 95
mux_sel
1
0
0
1
1
1
0
1
0
LED select
mux_clr
1
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
mux_map_next
1
0
0
1
1
1
0
1
1
0
0
0
0
0
0
0
mux_map_prev
1
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
mux_ld_next
1
0
0
1
1
1
0
1
1
0
0
0
0
0
0
1
mux_ld_prev
1
0
0
1
1
1
0
1
1
1
0
0
0
0
0
1
mux_ld_addr
1
0
0
1
1
1
1
1
0
SRAM address 0-95
mux_map_addr
1
0
0
1
1
1
1
1
1
SRAM address 0-95



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