LP5523 datasheet(8/61 Pages) TI2

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LP5523

SNVS550E – SEPTEMBER 2009 – REVISED JANUARY 2017

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(1)

The Electrical Characteristics tables list ensured specifications under Recommended Operating Conditions except as otherwise modified

or specified by the Electrical Characteristics conditions and/or notes. Typical specifications are estimations only and are not ensured.

(2)

All voltages are with respect to the potential at the GND pin.

(3)

Minimum and maximum limits are ensured by design, test, or statistical analysis.

(4)

Minimum and maximum limits are ensured by design, test, or statistical analysis.

(5)

Specification is ensured by design and is not tested in production. VEN = 1.65 V to VDD.

6.11 Serial Bus Timing Parameters (SDA, SCL)

Unless otherwise noted limits apply for TA = 25°C. See

(1) (2) (3) (4) (5)

MIN

MAX

UNIT

fSCL

Clock frequency

400

kHz

Hold time (repeated) START condition

0.6

µs

Clock low time

1.3

µs

Clock high time

600

Setup TIME FOR A REPEATED START condition

600

Data hold time

Data setup time

100

Rise time of SDA and SCL

20+0.1 Cb

300

Fall time of SDA and SCL

15+0.1 Cb

300

Set-up time for STOP condition

600

Bus free time between a STOP and a START condition

1.3

µs

Capacitive load parameter for each bus line.

Load of one picofarad corresponds to one nanosecond.

200

Figure 1. External Clock Signals

Figure 2. Serial Bus Timing Diagram

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