TAS5624A

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SLAS844A – MAY 2012 – REVISED JANUARY 2016

10.2.1.1 Design Requirements

Table 5 lists the design parameters of Figure 16.

Table 5. Design Requirements

PARAMETER

VALUE

Digital regulator supply

12 V

Full-bridge power supply

12 V to 38 V

PWM modulator

TAS5558

Output filters

Inductor-capacitor lowpass filter

Speaker

2.5

Ω minimum

10.2.1.2 Detailed Design Procedure

Using Figure 16 as a guide, integrate the hardware into the system schematic.

Following the recommended component placement, schematic layout and routing given in Layout Example,

integrate the device and its supporting components into the system PCB file.

•

The most critical section of the circuit is the power supply inputs, the amplifier output signals, and the high-

frequency signals which go to the serial audio port. TI recommends that these be constructed to ensure they

are given precedent as design trade-offs are made.

•

For questions and support go to the E2E Forum at www.e2e.ti.com. If it is necessary to deviate from the

recommended layout, please visit the E2E Forum to request a layout review.

10.2.1.2.1

Pin Connections

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Pin 1 - GVDD_AB is the gate-drive voltage for half-bridges A and B. It needs a 3.3-

Ω isolation resistor and a

0.1-µF decoupling capacitor.

•

Pin 2 - VDD is the supply for internal voltage regulators AVDD and DVDD. It needs a 10-µF bulk capacitor

and a 0.1-µF decoupling capacitor.

•

Pin 3 - Roc adjust is the overcurrent programming resistor. Depending on the application, this resistor can be

between 24 k

Ω to 68 kΩ.

•

Pin 4 - RESET pin when asserted, it keeps outputs Hi-Z and no PWM switching. This pin can be controlled by

a microprocessor.

•

Pins 5 and 6 - These are PWM(+) and PWM(–) pins with signals provided by a PWM modulator such as the

TAS5558. These are PWM differential pairs.

•

Pin 7 - Start-up ramp capacitor must be 1 µF for SE configuration.

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Pin 8 - Digital output supply pin is connected to 1-µF decoupling capacitor.

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Pins 9-12 - Ground pins are connected to board ground.

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Pin 13 - Analog output supply pin is connected to 1-µF decoupling capacitor.

•

Pins 14 and 15 - These are PWM(+) and PWM(–) pins with signals provided by a PWM modulator such as

the TAS5558. These are PWM differential pair.

•

Pin 16 - Fault pin can be monitored by a microcontroller through GPIO pin. System can decide to assert reset

or shutdown.

•

Pin 17 - Overtemperature warning pin can be monitored by a microcontroller through a GPIO pin. System can

decide to turn on fan or lower output power.

•

Pin 18 - Output clip indicator can be monitored by a microcontroller through a GPIO pin. System can decide

to lower the volume.

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Pins 19-21 - Mode pins set the input and output configurations. For this configuration M1-M3 are grounded.

These mode pins must be hardware configured, such as, not through GPIO pins from a microcontroller.

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Pin 22 - GVDD_CD is the gate-drive voltage for half-bridges C and D. This pin needs a 3.3-

Ω isolation

resistor and a 0.1-µF decoupling capacitor.

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Pins 23, 24, 43, 44 - Bootstrap pins for half-bridges A, B, C, and D. Connect 33 nF from this pin to

corresponding output pins.

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Pins 25, 26, 33, 34, 41, 42 - These ground pins must be used to ground decoupling capacitors from PVDD_X.

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Pins 27, 28, 32, 35, 39, 40 - Output pins from half-bridges A, B, C, and D. Connect appropriate bootstrap

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