ZL40220

Data Sheet

8

Microsemi Corporation

3.2

Clock Input Termination

The ZL40220 is adaptable to support different types of differential and singled-ened input signals depending on the

passive components used in the input termination. The application diagrams in the following figures allow the

ZL40220 to accept LVPECL, LVDS, CML, HCSL and single-ended inputs.

50 

Ohms

50 

Ohms

VDD_driver

VDD

VDD_driver=3.3V: R1 = 50 ohm

Not recommended for VDD_driver=2.5V

ZL40220

clk_p

clk_n

Zo = 50 Ohms

Zo = 50 Ohms

R1

LVPECL

Driver

Figure 4 - LVPECL Input DC Coupled Thevenin Equivalent

VDD_driver

R2

R2

R1

R1

VDD_driver

VDD

For VDD_Rx =3.3V: R1=82 Ohms,  R2=127 Ohms

For VDD_Rx=2.5V:R1= 62.5 Ohms, R2= 250 Ohms

ZL40220

clk_p

clk_n

Zo = 50 Ohms

Zo = 50 Ohms

LVPECL

Driver

Figure 5 - LVPECL Input DC Coupled Parallel Termination