TMS320VC33 datasheet(40/59 Pages) TI2

40 / 59 page

TMS320VC33

DIGITAL SIGNAL PROCESSOR

SPRS087E -- FEBRUARY 1999 -- REVISED JANUARY 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251--1443

reset timing

RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings

are met, the exact sequence shown in Figure 28 occurs; otherwise, an additional delay of one clock cycle is

possible.

The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.

Resetting the device initializes the bus control register to seven software wait states and therefore results in slow

external accesses until these registers are initialized.

HOLD is a synchronous input that can be asserted during reset. It can take nine CPU cycles before HOLDA

is granted.

The following tables define the timing parameters for the RESET signal.

timing requirements for RESET (see Figure 28)

VC33-120

VC33-150

UNIT

MIN

MAX

MIN

MAX

UNIT

tsu(RESET-EXTCLKL)

Setup time, RESET before EXTCLK low

P--7†

P--7

tsu(RESETH-H1L)

Setup time, RESET high before H1 low and after ten H1 clock cycles

† P=tc(EXTCLK)

switching characteristics over recommended operating conditions for RESET (see Figure 28)

PARAMETER

VC33-120

VC33-150

UNIT

PARAMETER

MIN

MAX

MIN

MAX

UNIT

td(EXTCLKH-H1H)

Delay time, EXTCLK high to H1 high

td(EXTCLKH-H1L)

Delay time, EXTCLK high to H1 low

td(EXTCLKH-H3L)

Delay time, EXTCLK high to H3 low

td(EXTCLKH-H3H)

Delay time, EXTCLK high to H3 high

tdis(H1H-DZ)

Disable time, data (high impedance) from H1 high‡

tdis(H3H-AZ)

Disable time, address (high impedance) from H3 high

td(H3H-CONTROLH)

Delay time, H3 high to control signals high

td(H1H-RWH)

Delay time, H1 high to R/W high

td(H1H-IACKH)

Delay time, H1 high to IACK high

tdis(RESETL-ASYNCH)

Disable time, asynchronous reset signals disabled (high impedance)

from RESET low§

‡ High impedance for Dbus is limited to nominal bus keeper ZOUT =15kΩ.

§ Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.

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