USB3300_07 datasheet(29/55 Pages) SMSC

29 / 55 page

Hi-Speed USB Host, Device or OTG PHY with ULPI Low Pin Interface

Datasheet

SMSC USB3300

Revision 1.08 (11-07-07)

DATASHEET

6.1.5.1

ULPI Register Write

A ULPI register write operation is given in Figure 6.4. The TXD command with a register write

DATA[7:6] = 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the

TXD CMD byte.

To write to a register, the Link will wait until DIR is low, and at T0, drive the TXD CMD on the databus.

At T2 the PHY will drive NXT high. On the next rising clock edge, T3, the Link will write the register

data. At T4 the PHY will accept the register data and the Link will drive an Idle on the bus and drive

STP high to signal the end of the data packet. Finally, at T5, the PHY will latch the data into the register

and drive NXT low. The Link will pull STP low.

NXT is used to control when the Link drives the register data on the bus. DIR is low throughout this

transaction since the PHY is receiving data from the Link. STP is used to end the transaction and data

is registered after the de-assertion of STP. After the write operation completes, the Link must drive a

ULPI Idle (00h) on the data bus or the USB3300 may decode the bus value as a ULPI command.

10b

XXXXXXb

Immediate Register Write Command where

DATA[5:0] = 6-bit register address

11b

XXXXXXb

Immediate Register Read Command where

DATA[5:0] = 6-bit register address

Figure 6.4 ULPI Register Write

Table 6.4 ULPI TXD CMD Byte Encoding (continued)

COMMAND NAME

CMD

BITS[7:6]

CMD BITS[5:0]

COMMAND DESCRIPTION

DIR

CLK

DATA[7:0]

STP

NXT

TXD CMD

(reg write)

Idle

Reg Data[n]

Idle

ULPI Register

Reg Data [n-1]

Reg Data [n]

USB3300 데이터시트(PDF) 29 Page - SMSC Corporation

USB3300 데이터시트(HTML) 29 Page - SMSC Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

데이터시트 다운로드

링크 URL