CLASS AB

CONTROL

BIAS

CONTROL

MP3

MP4

MP1

MP2

MN2

MN4

MN3

MN1

Q2

Q1

Q3

Q4

Q5

Q6

OUT

IN

+

V

-

SD

IN

-

IN

VBIAS

VBIAS

IP

V

+

Copyright © 2016, Texas Instruments Incorporated

16

LMV712-N, LMV712-N-Q1

SNOS534J – FEBRUARY 2001 – REVISED NOVEMBER 2016

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Product Folder Links: LMV712-N LMV712-N-Q1

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Copyright © 2001–2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The LMV712-N features low voltage, low power, and rail-to-rail output operational amplifiers designed for low-

voltage portable applications.

7.2 Functional Block Diagram

7.3 Feature Description

Rail-to-rail input is achieved by using in parallel, one NMOS differential pair (MN1 and MN2) and one PMOS

differential pair (MP1 and MP2). When the common mode input voltage (VCM) is near V

+, the NMOS pair is on

and the PMOS pair is off. When VCM is near V

−, the NMOS pair is off and the PMOS pair is on. When V

CM is

between V+ and V−, internal logic decides how much current each differential pair receives. This special logic

ensures stable and low distortion amplifier operation within the entire common mode voltage range.

Because both input stages have their own offset voltage (VOS) characteristic, the offset voltage of the LMV712-N

becomes a function of VCM. VOS has a crossover point at 1.4 V above V

− (see Figure 3). Caution must be taken

in situations where input signal amplitude is comparable to VOS value or the design requires high accuracy. In

these situations, it is necessary for the input signal to avoid the crossover point.

The current coming out of the input differential pairs gets mirrored through two folded cascode stages (Q1, Q2,

Q3, Q4) into the class AB control block. This circuitry generates voltage gain, defines the dominant pole of the op

amp and limits the maximum current flowing at the output stage. MN3 introduces a voltage level shift and acts as

a high impedance to low impedance buffer.