V

OUT

C

L

V

IN

R

ISO

R

L

R

F

C

F

V

OUT

C

L

V

IN

R

ISO

18

LMV712-N, LMV712-N-Q1

SNOS534J – FEBRUARY 2001 – REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: LMV712-N LMV712-N-Q1

Submit Documentation Feedback

Copyright © 2001–2016, Texas Instruments Incorporated

Device Functional Modes (continued)

Figure 32. Driving Heavy Capacitive Loads

In Figure 32, the isolation resistor RISO and the load capacitor CL form a pole to increase stability by adding more

phase margin to the overall system. The desired performance depends on the value of RISO. The bigger the RISO

resistor value, the more stable VOUT is. But the DC accuracy is degraded when the RISO gets bigger. If there were

a load resistor in the application, the output voltage would be divided by RISO and the load resistor.

Figure 33 is an improvement to the one in Figure 32 because it provides DC accuracy as well as AC stability. In

Figure 33, RF provides the DC accuracy by using feed-forward techniques to connect VIN to RL. CF and RISO

serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back

to the inverting input of the amplifier, thereby preserving phase margin in the overall feedback loop. Increased

capacitive drive is possible by increasing the value of CF. This in turn slows down the pulse response.

Figure 33. Enhanced DC Accuracy

7.4.3 Latchup

CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR (silicon controlled rectifier)

effects. The input and output pins look similar to the gate of the SCR. There is a minimum current required to

trigger the SCR gate lead. The LMV712-N is designed to withstand 150-mA surge current on all the pins. Some

resistive method must be used to isolate any capacitance from supplying excess current to the pins. In addition,

like an SCR, there is a minimum holding current for any latchup mode. Limiting current to the supply pins also

inhibits latchup susceptibility.