ADS8317

SBAS356D – JUNE 2007 – REVISED OCTOBER 2009 .................................................................................................................................................... www.ti.com

Short Cycling

POWER DISSIPATION

Another way to save power is to use the CS signal to

The architecture of the converter, the semiconductor

short-cycle the conversion. The ADS8317 places the

fabrication process, and a careful design allow the

latest data bit on the DOUT line as it is generated;

ADS8317 to convert at up to a 250kHz rate while

therefore, the converter can easily be short-cycled.

requiring very little power. However, for the absolute

This term means that the conversion can be

lowest power dissipation, there are several things to

terminated at any time. For example, if only 14 bits of

keep in mind.

the conversion result are needed, then the conversion

The power dissipation of the ADS8317 scales directly

can be terminated (by pulling CS high) after the 14th

with conversion rate. Therefore, the first step to

bit has been clocked out.

achieving the lowest power dissipation is to find the

This technique can also be used to lower the power

lowest conversion rate that satisfies the system

dissipation (or to increase the conversion rate) in

requirements.

those applications where an analog signal is being

In addition, the ADS8317 goes into Power-Down

monitored until some condition becomes true. For

mode under two conditions: when the conversion is

example, if the signal is outside a predetermined

complete and whenever CS is high (see the Timing

range, the full 16-bit conversion result may not be

Characteristics section). Ideally, each conversion

needed. If so, the conversion can be terminated after

should occur as quickly as possible, preferably at a

the first n bits, where n might be as low as 3 or 4.

6.0MHz clock rate. This way, the converter spends

This technique results in lower power dissipation in

the longest possible time in power-down mode. This

both the converter and the rest of the system

is very important because the converter not only uses

because they spend more time in power-down mode.

power on each DCLOCK transition (as is typical for

digital CMOS components), but also uses some

POWER-ON RESET

current

for

the

analog

circuitry,

such

as

the

comparator. The analog section dissipates power

The ADS8317 bias circuit is self-starting. There may

continuously until power-down mode is entered.

be a static current (approximately 1.5mA with VDD =

5V) after power-on, unless the circuit is powered

Figure

9

and

Figure

27

illustrate

the

current

down. It is recommended to run a single test

consumption of the ADS8317 versus sample rate. For

conversion (configured the same as any regular

these graphs, the converter is clocked at maximum

conversion) after the power supply reaches at least

speed regardless of the sample rate. CS is held high

2.4V to ensure the device is put into power-down

during the remaining sample period.

mode.

There

is

an

important

distinction

between

the

power-down mode that is entered after a conversion

is complete and the full power-down mode that is

enabled when CS is high. CS low only shuts down

the analog section. The digital section completely

shuts down only when CS is high. Thus, if CS is left

low at the end of a conversion, and the converter is

continually clocked, the power consumption is not as

low as when CS is high.

22

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