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ADS8317IB 데이터시트(PDF) 31 Page - Texas Instruments |
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ADS8317IB 데이터시트(HTML) 31 Page - Texas Instruments |
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31 / 37 page ![]() www.ti.com EXAMPLE BOARD LAYOUT 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND 8X (1.4) 8X (0.45) 6X (0.65) (4.4) (R0.05) TYP VSSOP - 1.1 mm max height DGK0008A SMALL OUTLINE PACKAGE 4214862/A 04/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. 9. Size of metal pad may vary due to creepage requirement. TM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SYMM SYMM 1 4 5 8 SEE DETAILS 15.000 METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED |
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