6 Specifications

6.1 Absolute Maximum Ratings

see (1)

MIN

MAX

UNIT

Supply voltage

VDD

Supply voltage for LVCMOS core logic(2)

Supply voltage for LPSDR low speed interface

–0.5

2.3

V

VDDI

Supply voltage for SubLVDS receivers(2)

–0.5

2.3

V

VOFFSET

Supply voltage for HVCMOS and micromirror electrode(2) (3)

–0.5

11

V

VBIAS

Supply voltage for micromirror electrode(2)

–0.5

19

V

VRESET

Supply voltage for micromirror electrode(2)

–15

0.5

V

| VDDI–VDD |

Supply voltage delta (absolute value)(4)

0.3

V

| VBIAS–

VOFFSET |

Supply voltage delta (absolute value)(5)

11

V

| VBIAS–

VRESET |

Supply voltage delta (absolute value)(6)

34

V

Input voltage

Input voltage for other inputs LPSDR(2)

–0.5

VDD + 0.5

V

Input voltage for other inputs SubLVDS(2) (7)

–0.5

VDDI +

0.5

V

Input pins

| VID |

SubLVDS input differential voltage (absolute value)(7)

810

mV

IID

SubLVDS input differential current

10

mA

Clock frequency

ƒclock

Clock frequency for low speed interface LS_CLK

130

MHz

ƒclock

Clock frequency for high speed interface DCLK

620

MHz

Environmental

TARRAY and

TWINDOW

Temperature – operational (8)

–20

90

°C

Temperature – non-operational(8)

–40

90

°C

TDP

Dew Point Temperature - operating and non-operating (non-

condensing)

81

°C

|TDELTA|

Absolute Temperature delta between any point on the window edge

and the ceramic test point TP1(9)

30

°C

(1)

Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and

this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2)

All voltage values are with respect to the ground terminals (VSS). The following power supplies are all required to operate the DMD:

VDD, VDDI, VOFFSET, VBIAS, and VRESET. All VSS connections are also required.

(3)

VOFFSET supply transients must fall within specified voltages.

(4)

Exceeding the recommended allowable absolute voltage difference between VDDI and VDD may result in excessive current draw.

(5)

Exceeding the recommended allowable absolute voltage difference between VBIAS and VOFFSET may result in excessive current

draw.

(6)

Exceeding the recommended allowable absolute voltage difference between VBIAS and VRESET may result in excessive current

draw.

(7)

This maximum input voltage rating applies when each input of a differential pair is at the same voltage potential. Sub-LVDS differential

inputs must not exceed the specified limit or damage may result to the internal termination resistors.

(8)

The highest temperature of the active array (as calculated by the Section 7.6) or of any point along the Window Edge as defined in

Figure 7-1. The locations of thermal test points TP2, TP3, TP4, and TP5 in Figure 7-1 are intended to measure the highest window

edge temperature. If a particular application causes another point on the window edge to be at a higher temperature, that point should

be used.

(9)

Temperature delta is the highest difference between the ceramic test point 1 (TP1) and anywhere on the window edge as shown in

Figure 7-1. The window test points TP2, TP3, TP4, and TP5 shown in Figure 7-1 are intended to result in the worst case delta. If a

particular application causes another point on the window edge to result in a larger delta temperature, that point should be used.

DLP4710LC

DLPS178C – MAY 2020 – REVISED JULY 2023

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