ADV7182ABCPZ datasheet(7/102 Pages) AD

7 / 102 page

Data Sheet

ADV7182A

Rev. 0 | Page 7 of 102

TIMING SPECIFICATIONS

Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.62 V to 3.63 V, specified at operating temperature

range, unless otherwise noted.

Table 3.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SYSTEM CLOCK AND CRYSTAL

Nominal Frequency

28.63636

MHz

Frequency Stability

±50

ppm

I2C PORT

SCLK Frequency

400

kHz

SCLK Minimum Pulse Width

High

0.6

μs

Low

1.3

μs

Hold Time (Start Condition)

0.6

μs

Setup Time (Start Condition)

0.6

μs

SDATA Setup Time

100

SCLK and SDATA Rise Times

300

SCLK and SDATA Fall Times

300

Setup Time for Stop Condition

0.6

μs

RESET FEATURE

RESET Pulse Width

CLOCK OUTPUTS

LLC Mark Space Ratio

t9:t10

45:55

55:45

% duty cycle

DATA AND CONTROL OUTPUTS

Data Output Transitional Time

t11

Negative clock edge to start of valid data

(tACCESS = t10 − t11)

3.8

t12

End of valid data to negative clock edge

(tHOLD = t9 + t12)

6.9

Timing Diagrams

Figure 2. I2C Timing Diagram

Figure 3. Pixel Port and Control Output Timing Diagram

SDATA

SCLK

OUTPUT LLC

OUTPUTS P0 TO P7, HS,

VS/FIELD/SFL

t10

t11

t12

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