STW4810CHDRLF datasheet(15/78 Pages) STMICROELECTRONICS

부품명	STW4810CHDRLF

상세설명	Power management for multimedia processors

PDF	78 Pages

Scroll/Zoom	100%

제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

Logo

15 / 78 page

STw4810

Functional description

15/78

REQUEST_MC ball. STw4810 remains in internal oscillator mode until it receives the

external clock signal on MASTER_CLK ball.

EXT_CLK: When MASTER_CLK is detected, the STw4810 uses this clock as reference and

switches off its internal oscillator to save quiescent. MASTERCLK should remain connected

up to sleep mode.

Sleep: Sleep mode is required by multimedia processor by setting a PWREN at low level.

Then VDDOK is forced to 0, regulators (VCORE, VIO_VMEM) switch to sleep mode and

wait for PWREN at high level (

Figure 4).

Wake-up: From sleep mode, the multimedia processor requests to switch back to Normal

mode. Thus the device restarts its internal oscillator and then switches regulators from sleep

to normal mode and informs multimedia processor with VDDOK at high level (

Figure 4).

Note:

By default VAUX is in stand by mode, pdn_vaux = 0 (Table 18). It can be programmed in

normal mode only by asserted pdn_vaux bit to “1”.

STW4810CHDRLF 데이터시트(PDF) 15 Page - STMicroelectronics