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ADC32RF44IRMPR 데이터시트(PDF) 30 Page - Texas Instruments

부품명 ADC32RF44IRMPR
상세설명  ADC32RF44 Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter
PDF  135 Pages
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제조업체  TI2 [Texas Instruments]
홈페이지  https://www.ti.com
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ADC32RF44IRMPR 데이터시트(HTML) 30 Page - Texas Instruments

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CLKIN
SYSREF
(1)
1
st SYSREF pulse.
The input clock divider
is reset.
Time > tDLL + 2 x tSYSREF
MASK NCO SYSREF Register Bit
(2)
0
1 (The NCO and LMFC counter of the JESD
interface ignore the SYSREF pulses.)
Mask SYSREF to the NCO after
resetting the NCO phase.
The NCO phase is reset here for
the last time.
Then, the NCO mask is set high to
ignore further SYSREF pulses.
30
ADC32RF44
SBAS809A – FEBRUARY 2017 – REVISED MARCH 2017
www.ti.com
Product Folder Links: ADC32RF44
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
(1)
fS = sampling (device) clock frequency.
(2)
LCM = least-common multiple.
(3)
K = number of frames per multi-frame.
(4)
S = samples per frame.
(5)
D = decimation ratio.
2. SYSREF is applied as a periodic pulse.
Figure 70 shows how SYSREF can be applied as a continuous periodic waveform.
tSYSREF is a period of the SYSREF waveform.
Alternatively, the SYSREF buffer can be powered down using the PDN SYSREF bit.
Figure 70. SYSREF Used as a Periodic Waveform
After applying the SYSREF signal, DLL must be allowed to lock, and the NCO phase and LMFC counter
must be allowed to reset by waiting for at least the tDLL (40 µs) + 2 × tSYSREF time. Then, the SYSREF going
to the NCO and JESD can be masked by setting the MASK NCO SYSREF register bit.
9.3.3.2 Frequency of the SYSREF Signal
When SYSREF is a periodic signal, its frequency is required to be a sub-harmonic of the internal local multi-
frame clock (LMFC) frequency, as described in Equation 1. The LMFC frequency is determined by the selected
decimation, frames per multi-frame setting (K), samples per frame (S), and device input clock frequency.
SYSREF = LMFC / N
where
•
N is an integer value (1, 2, 3, and so forth)
(1)
In order for the interleaving correction engine to synchronize properly, the SYSREF frequency must also be a
multiple of fS / 64. Table 2 provides a summary of the valid LMFC clock settings.
Table 2. . SYSREF and LMFC Clock Frequency
OPERATING MODE
LMFS SETTING
LMFC CLOCK FREQUENCY
SYSREF FRQUENCY
Bypass mode
82820
fS
(1) / (20 × K)
fS / (N × LCM
(2) (64, 20 × K(3)))
Bypass mode
8224
fS/(4 × K)
fS / (N × LCM (64, 4 × K))
Decimation
Various
fS / (D × S
(4) × K)
fS / (N × LCM (64, D
(5) × S × K))
The SYSREF signal is recommended to be a low-frequency signal less than 5 MHz in order to reduce coupling to
the signal path both on the printed circuit board (PCB) as well as internal to the device.



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