Bus Signal Line Load

The total capacitance CL of each line of the eMMC bus is the sum of the bus master capacitance CHOST, the bus

capacitance CBUS itself and the capacitance CDEVICE of eMMC connected to this line:

CL = CHOST + CBUS + CDEVICE

The sum of the host and bus capacitances must be under 20pF.

Table 20: Signal Line Load

Parameter

Symbol

Min.

Max.

Unit

Remark

Pull-up resistance for

CMD

RCMD

4.7

50

Kohm

to prevent bus floating

Pull-up resistance for

DAT0–7

RDAT

10

50

Kohm

to prevent bus floating

Pull-up resistance for

RST_n

RRST_n

4.7

50

Kohm

It is not necessary to put pull-up resistance

on RST_n (H/W rest) line

if host does not use H/W reset. (Extended CSD

register [162] = 0 b)

Bus signal line

capacitance

CL

30

pF

Single Device

Single Device

capacitance

CBGA

6

pF

Maximum signal line

inductance

16

nH

Impedance on CLK / CMD

/ DAT0~7

45

55

ohm

Impedance match

Serial’s resistance on CLK

line

SRCLK

0

47

ohm

Serial’s resistance on

CMD / DAT0~7 line

SRCMD

SRDAT0~7

0

47

ohm

VCCQ decoupling capacitor

CVCCQ1

4.7

10

μF

It should be located as close as possible to

the balls defined in order to minimize

connection parasitic

CVCCQ2

0.1

0.1

VCC capacitor value

CVCC1

4.7

10

μF

It should be located as close as possible to

the balls defined in order to minimize

connection parasitic

CVCC2

0.1

0.1

VDDi capacitor value

CREG

1+0.1

2.2+0.1

μF

To stabilize regulator output to controller core

logics. It should be located as close as

possible to the balls defined in order to

minimize connection parasitic

Confidential

-22

／42-

Rev.1.0 July 2023

32GB/64GB/128GB eMMC