STM32WL33C8 datasheet(17/91 Pages) STMICROELECTRONICS

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3.7

Reset management

The STM32WL33xx offers two resets:

•

PORESETn: this reset is provided by the APMU analog power management unit block and corresponds to

a POR or BOR root cause. It is linked to power voltage ramp-up or ramp-down. This reset impacts all

resources of the STM32WL33xx device.

Exit from Shutdown mode is equivalent to a POR/BOR and thus generates a PORESETn.

•

The PADRESETn (system reset): this reset is built through several sources:

–

PORESETn

–

Reset due to the watchdog The STM32WL33xx embeds a watchdog timer, which may be used to

recover from software crashes.

–

Reset due to CPU Lockup. The Cortex-M0+ generates a lockup to indicate the core is in the lock-up

state resulting from an unrecoverable exception. The lock-up reset is masked if a debugger is

connected to the Cortex-M0+.

–

Software system reset. The system reset request is generated by the debug circuitry of the Cortex-

M0+. The debugger sets the SYSRESETREQ bit of the application interrupt and reset control register

(AIRCR). This system reset request through the AIRCR can also be done by the embedded software

(into the hardfault handler for instance).

–

Reset from the NRSTn external pin The NRSTn pin toggles to inform that a reset has occurred.

The PADRESETn resets all resources of the STM32WL33xx, except:

•

debug features

•

flash controller key management

•

RTC timer

•

power controller unit

•

part of the RCC registers

The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case

of reset from the RSTN external pad, the reset pulse is generated when the pad is asserted low.

STM32WL33xx

Functional overview

DS14221 - Rev 5

page 17/91

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