| 전자부품 데이터시트 검색엔진 |
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CDCE421ARGET 데이터시트(PDF) 16 Page - Texas Instruments |
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CDCE421ARGET 데이터시트(HTML) 16 Page - Texas Instruments |
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16 / 29 page ![]() Appendix A: Test Configurations LVDS 100 W LVDS LVPECL 50 W 50 W LVPECL VCC 2V - LVDS 50 W PhaseNoise Analyzer LVPECL 150 W 150 W 150 W PhaseNoise Analyzer CDCE421A SCAS873 – APRIL 2009..................................................................................................................................................................................................... www.ti.com Test setups are used to characterize the CDCE421A device in both ac- and dc-termination. Figure 5 through Figure 8 illustrate all four setups used to terminate the clock signal driven by the device under test. Figure 5. LVDS DC Termination Test Configuration Figure 6. LVPECL DC Termination Test Configuration Figure 7. LVDS AC Termination Test Configuration Figure 8. LVPECL AC Termination Test Configuration 16 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): CDCE421A |
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