VDD

R

INT

Clock Generator:

VDD

XIN

XOUT

R

s

R

+ R

= 50

INT

s

W

R = 100

1

W

C = 0.1

F

m

Z

= 50

o

W

R = 100

2

W

Crystal

C

1

C

2

XIN

XOUT

R

OPTIONAL

CDCLVC1310

SCAS917E – JULY 2011 – REVISED JANUARY 2014

www.ti.com

Figure 12. Crystal Reference Input

The input XIN can accept single-ended LVCMOS signals in two configurations. It is possible to overdrive the

oscillator stage or to use a pure LVCMOS input (see Table 1). If overdriving the oscillator stage, it is necessary

to ac-couple the input with a capacitor (see Figure 13). Otherwise, if selecting the bypass, there is no

requirement for a coupling capacitor. Additional measurements and information about crystal oscillator input and

limiting the drive level are available in the applications report Crystal Oscillator Performance of the CDCLVC1310

(SCAA119).

NOTE

If using the overdrive or bypass mode, the device is functional, but may not meet its ac

parameters.

Figure 13. Single-Ended Crystal Input

Phase-Noise Performance

The CDCLVC1310 provides ultralow phase-noise outputs (noise floor = –170 dBc/Hz) if it has an attached

crystal. Figure 14 shows the phase-noise plot of the CDCLVC1310 with a 25-MHz crystal at VDD = VDDO = 3.3 V

and room temperature.

14

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