| 전자부품 데이터시트 검색엔진 |
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L9969X 데이터시트(PDF) 5 Page - STMicroelectronics |
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L9969X 데이터시트(HTML) 5 Page - STMicroelectronics |
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5 / 70 page ![]() Figure 5. L9969T - pin connection (top view) PSSO36 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 OUT22 PWM2 SI NSS1 SCK OUT11 PGND1 DIR2 DIS2 VS2 VS2 VDD2 NC SO AGND2 GNDNABE2 NABE1 CF1 PGND2 OUT21 VS1 DIS1 DIR1 PWM1 OUT12 NC NSS2 NC NC CF2 NABE2 VS1 NDNABE1 AGND1 TEST VDD1 1.3 Pin definitions and functions Table 1. L9969S pin-out Pin # Pin name Description I/O type Class 1 NC Not connected - - 2 PGND Power Ground of H-bridge G Global 3 OUT1 Output 1 of H-bridge O Global 4 NC Not connected - - 5 SCK SPI-Clock input of H-bridge I Local 6 NSS SPI-Slave Select input of H-bridge I Local 7 SI SPI-Slave In (data receive) input of H-bridge I Local 8 SO SPI-Slave Out (data transceive) output of H-bridge O Local 9 CF Current feedback of H-bridge. Signal is proportional to the positive current in active LS-transistor of H-bridge. O Local 10 NABE Bidirectional Enable/Disable in-/output. Open-drain output, switched to low at VDD over and undervoltage condition. Low level disables the power stage. (OUT1 and OUT2) I/O Local 11 GNDNABE Reference Ground of VDD-monitoring. G Local 12 NC Not connected - - 13 NC Not connected - - L9969x Block diagram and pin description DS14029 - Rev 6 page 5/70 |
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