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ISO7420FEDRG4 데이터시트(PDF) 24 Page - Texas Instruments |
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ISO7420FEDRG4 데이터시트(HTML) 24 Page - Texas Instruments |
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24 / 35 page ![]() T = 25°C, V = V = 3.3 V, A CC1 CC2 Pattern: PRBS 2 -1 7 T = 25°C, V 1 = V 2 = 3.3 V, Pattern: PRBS 2 -1 A CC CC 7 ISO7420E, ISO7420FE, ISO7421E, ISO7421FE SLLSE45F – DECEMBER 2010 – REVISED JULY 2015 www.ti.com Typical Application (continued) 9.2.3 Application Curves Figure 27. ISO7420FE Typical Eye Diagram at 100 MBPS, Figure 26. ISO7420FE Typical Eye Diagram at 50 MBPS, 3.3 V Operation 3.3 V Operation 10 Power Supply Recommendations To ensure reliable operation at all data rates and supply voltages, a 0.1 µF bypass capacitor is recommended at input and output supply pins (VCC1 and VCC2). The capacitors should be placed as close to the supply pins as possible. If only a single primary-side power supply is available in an application, isolated power can be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501. For such applications, detailed power supply design and transformer selection recommendations are available in SN6501 datasheet (SLLSEA0). 24 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated Product Folder Links: ISO7420E ISO7420FE ISO7421E ISO7421FE |
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