EF9345 datasheet(33/38 Pages) STMICROELECTRONICS

33 / 38 page

MICROPROCESSOR ACCESS COMMANDS

A microprocessor bus cycle may transfer one byte

from/to the microprocessor to/from a directly ad-

dressable register. These registers provide an in-

direct access :

- To/from 5 on-chip indirect registers : ROR, DOR,

MAT, PAT and TGS.

- To/from the private memory.

Due to address/datamultiplexing, a bus cycle is a

2 phase process (see Timing diagram 1 or Timing

diagram 2).

Address Phase

The falling edge of AS latches to AD(0:7) bus state

and CS signal into the temporary A address register

(Figure 36).

- A(0:2) = i :

This register index designates one out of 8 direct

access registers Ri.

- A3 = XQR :

This is the execution request bit.

- A(4:7) = ASN :

This is the Auto-Selection Nibble

- A8 = LCS :

This is the latched value of CS input pin.

EF9345 is selected when the following condition is

met : ASN = 2(Hexa) and LCS = 0.

Therefore, EF9345 is mapped in the hexadecimal

microprocessor addressing space form XX20 to

XX2F, where XX is up to the user. Xhen EF9345 is

not selected, its AD bus pins float and no register

can be modified.

DATA

REGISTERS

AUXILIARY

POINTER

MAIN

POINTER

65432

765

43210

65432

CODE

PAR

D’

B’

X’

Y’

COMMAND

(write only)

STATUS

(read only)

V sync status

a (X’ = 39)

m (X = 39)

Alarm

Busy

Figure 36 : Direct Access Registers

432

ADDRESS

(temporary)

Index register

Execution request (XOR)

Auto select nibble

(compared to 0010)

LCS (latched CS)

Figure 35

EF9345

33/38

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