SPC563M60L7 datasheet(25/128 Pages) STMICROELECTRONICS

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SPC563M64x, SPC563M60x

Overview

127

2.3.8

ECSM

The error correction status module provides status information regarding platform memory

errors reported by error-correcting codes.

2.3.9

Flash

Devices in the SPC563Mxx family provide up to 1.5 MB of programmable, non-volatile, flash

memory. The non-volatile memory (NVM) can be used for instruction and/or data storage.

The flash module includes a Fetch Accelerator, that optimizes the performance of the flash

array to match the CPU architecture and provides single cycle random access to the Flash

@ 80 MHz. The Flash module interfaces the system bus to a dedicated Flash memory array

controller. For CPU ‘loads’, DMA transfers and CPU instruction fetch, it supports a 64-bit

data bus width at the system bus port, and a 128-bit read data interface to Flash memory.

The module contains a four-entry, 128-bit prefetch buffer and a prefetch controller which

prefetches sequential lines of data from the Flash array into the buffer. Prefetch buffer hits

allow no-wait responses. Normal Flash array accesses are registered and are forwarded to

the system bus on the following cycle, incurring three wait-states. Prefetch operations may

be automatically controlled, and are restricted to instruction fetch.

The Flash memory provides the following features:



Supports a 64-bit data bus for instruction fetch, CPU loads and DMA access. Byte,

halfword, word and doubleword reads are supported. Only aligned word and

doubleword writes are supported.



Fetch Accelerator

–

Architected to optimize the performance of the Flash with the CPU to provide

single cycle random access to the Flash up to 80 MHz system clock speed

–

Configurable read buffering and line prefetch support

–

Four line read buffers (128 bits wide) and a prefetch controller



Hardware and software configurable read and write access protections on a per-master

basis



Interface to the Flash array controller is pipelined with a depth of one, allowing

overlapped accesses to proceed in parallel for interleaved or pipelined flash array

designs



Configurable access timing allowing use in a wide range of system frequencies



Multiple-mapping support and mapping-based block access timing (0-31 additional

cycles) allowing use for emulation of other memory types



Software programmable block program/erase restriction control



Erase of selected block(s)



Read page size of 128 bits (four words)



ECC with single-bit correction, double-bit detection



Program page size of 64 bits (two words)



ECC single-bit error corrections are visible to software



Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte

address, due to ECC



Embedded hardware program and erase algorithm



Erase suspend

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