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STA109X 데이터시트(PDF) 75 Page - STMicroelectronics |
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STA109X 데이터시트(HTML) 75 Page - STMicroelectronics |
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75 / 127 page ![]() DS13319 Rev 2 75/127 STA108x, STA109x Electrical Characteristics 126 Figure 15. Wake Up (VDDOK timed) Table 41. Wake Up (VDDOK timed) Note: For the Wake-Up sequence VDDOK timed see Figure 15. Symbol Parameter Timing Unit Min. Max. t1 SR PWREN to last voltage stable - 174(1) 1. This value is programmable in the Power Management Unit. By default, at POR, is set to the maximum of 174 ms. ms t2 SR Last voltage stable to VDDOK > 0 - µs t3 SR PWREN to VDDOK - 174 ms t4 SR VDDOK to LVI(2) 2. The LVI signal has effect during the boot only if the LVIEn bit is set. If the LVIEn bit is set, the t4 timing, if respected, is the minimum timing that ensures that the PMU FSM reaches the ON state. If the LVIEn bit is set and an LVI event occurs before the timing t4, the PMU FSM directly moves back to the STAND-By state without reaching the ON state. 2- µs t5 SR VDDOK to SYSRSTn release > 0 - µs VDDIO_ON VDD_ON_VREG VDD VDD_IO VDDOK PWREN wake up event SYSRSTn (optional) See Figure 12 t1 t2 t3 t4 LVI (if enabled) t5 |
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