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STA109X 데이터시트(PDF) 76 Page - STMicroelectronics |
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STA109X 데이터시트(HTML) 76 Page - STMicroelectronics |
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76 / 127 page ![]() Electrical Characteristics STA108x, STA109x 76/127 DS13319 Rev 2 Figure 16. Wake Up (without VDDOK) Table 42. Wake Up Timings (without VDDOK) Note: For the Wake-Up sequence without VDDOK see Figure 16. Symbol Parameter Timing Unit Min. Max. t1 SR PWREN to last voltage stable - 174(1) 1. This value is programmable in the Power Management Unit. By default, at POR, is set to the maximum of 174 ms. ms t2 SR Last voltage stable to LVI(2) 2. The LVI signal has effect during the boot only if the LVIEn bit is set. If the LVIEn bit is set, the t4 timing, if respected, is the minimum timing that ensures that the PMU FSM reaches the ON state. If the LVIEn bit is set and an LVI event occurs before the timing t2, the PMU FSM directly moves back to the STAND-By state without reaching the ON state. 8000+2 - µs t3 SR Last Voltage Stable to SYSRTSn > 0 - µs VDDIO_ON VDD_ON_VREG VDD VDD_IO PWREN wake up event SYSRSTn (optional) See Figure 12 t1 t2 LVI (if enabled) t3 VDDOK (High) tSYSSRSTn |
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