STA1080 datasheet(92/127 Pages) STMICROELECTRONICS

부품명	STA1080

상세설명	Accordo2 family – Automotive dual core processor for car radio and display audio application

PDF	127 Pages

Scroll/Zoom	100%

제조업체	STMICROELECTRONICS [STMicroelectronics]

홈페이지	http://www.st.com

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92 / 127 page

Electrical Characteristics

STA108x, STA109x

92/127

DS13319 Rev 2

4.19.2

Clock Constraint

A frequency clock relationship must be always respected in the configuration of HCLK and

SQI_CLK. This condition must be respected to ensure that the system works correctly in all

voltage, temperature and process conditions.

PLL1 SSCG (Spread Spectrum Clock Generation) Disabled

Figure 31. PLL1 Clock Diagram (SSCG Disabled)

The constraint to be respected is:

PLL1 SSCG (Spread Spectrum Clock Generation) Enabled

Figure 32. PLL1 Clock Diagram (SSCG Enabled)

The constraint to be respected is:

If the Spread Spectrum clock modulation is applied in the configuration of PLL1, the real

clock will be modulated between HCLK and HCLKMIN, so the minimum frequency of HCLK

(HCLKMIN) will be lower than HCLK by 2 % or 4 % depending on the configured modulation

width. With respect to HCLK, the constraint is expressed as:

where SSCG = 0, 0.02, 0.04

HCLK

SQI_CLK

----------------------------



 1.15





HCLKMIN

SQI_CLK

----------------------------



 1.15





HCLK

SQI_CLK

----------------------------





1.15

1 SSCG

–

---------------------------





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