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STA1090 데이터시트(PDF) 91 Page - STMicroelectronics

부품명 STA1090
상세설명  Accordo2 family – Automotive dual core processor for car radio and display audio application
PDF  127 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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STA1090 데이터시트(HTML) 91 Page - STMicroelectronics

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DS13319 Rev 2
91/127
STA108x, STA109x
Electrical Characteristics
126
The SQI_CLK generation is controlled by the bits [2:1] of SRCM3_CLKDIV register of the
SRC-M3 peripheral. The field SRCM3_CLKDIV[2:1] = SQI_CLK_SEL decodes as follows:
Bit 2:1 SQI_CLK_SEL
0b00 = PLL2.FVCOBY2 divide by 4 is selected
0b01 = PLL2.FVCOBY2 divide by 3 is selected
0b10 = PLL2.PHI is selected
0b11 = Reserved
HCLK Clock Generation
The HCLK clock is the main clock of the system. This is the clock used by the bus matrix
and the AHB or APB bridges, for the VIC, for the system timers (MTU0 and MTU1), the
watchdog and the embedded static RAM (eSRAM). HCLK is generated dividing the PLL1
output clock according to the following picture:
Figure 30. PLL1 Clock Diagram
The clock selected for HCLK is controlled by bits [2:0] of the SRCM3_CR registers:
Bit 2:0 Mode Control
Bit [0]: Internal Oscillator
Bit [1]: External Oscillator
Bit [3]: Normal
When the system is running in Normal mode, Bit [3] is set and HCLK is generated by the
output of PLL1. HCLK can run up to 208 MHz.
PLL1
MXTAL
FVCOBY2
PHI
RING OSC
3,4,5,6
DIV
DIV
DCLK
HCLK
CLK_R4
SRCR4_CLKDIVCR[8] = DRAM_CLK_SYNC
SRCR4_CLKDIVCR[6:4] = SDRAM_DIV
SRC_CLKDIVCR[2:0]= HCLK_DIV
SRCR3_CR[2:0] = MODECR
SRCR3_CR[2:0] = MODECR
GAPGPS02600
4,5,6



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