MSP430FR2000IRLL datasheet(13/85 Pages) TI2

13 / 85 page

7.4 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if

the device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see

Section 9.11.15.

7.5 Connection of Unused Pins

Table 7-3 lists the correct termination of unused pins.

Table 7-3. Connection of Unused Pins

PIN(1)

POTENTIAL

COMMENT

Px.0 to Px.7

Open

Set to port function, output direction (PxDIR.n = 1)

RST/NMI

DVCC

47-kΩ pullup or internal pullup selected with 10-nF (1.1 nF) pulldown(2)

TEST

Open

This pin always has an internal pulldown enabled.

(1)

Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection

guidelines.

(2)

The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like

FET interfaces or GANG programmers.

7.6 Buffer Type

Table 7-4 defines the pin buffer types that are listed in Table 7-1.

Table 7-4. Buffer Type

BUFFER TYPE

(STANDARD)

NOMINAL

VOLTAGE

HYSTERESIS

PU OR PD

NOMINAL

PU OR PD

STRENGTH

(µA)

OUTPUT DRIVE

STRENGTH

(mA)

OTHER

CHARACTERISTICS

LVCMOS

3.0 V

Y(1)

Programmable

See Section

8.12.4

See Section

8.12.4.3

Analog

3.0 V

N/A

See the analog modules in

Section 8 for details.

Power (DVCC)

3.0 V

N/A

SVS enables hysteresis on

DVCC.

Power (AVCC)

3.0 V

N/A

(1)

Only for input pins

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MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000

SLASE78E – AUGUST 2016 – REVISED JUNE 2021

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