IS25LE512M-RHLA3:P-TY datasheet(25/189 Pages) ISSI

부품명	IS25LE512M-RHLA3:P-TY

상세설명	SERIAL FLASH MEMORY 133/112MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

PDF	189 Pages

Scroll/Zoom	100%

제조업체	ISSI [Integrated Silicon Solution, Inc]

홈페이지	http://www.issi.com

Logo

25 / 189 page

IS25LE512M

IS25WE512M

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A6

06/16/2025

Note: A Chip Erase (CER) instruction will be ignored unless

all the Block Protection Bits are “0”s.

SRWD bit: The Status Register Write Disable (SRWD) bit operates in conjunction with the Write Protection (WP#)

signal to provide a Hardware Protection Mode. When the SRWD is set to “0”, the Status Register is not write-

protected. When the SRWD is set to “1” and the WP# is pulled low (VIL), the bits of Status Register (SRWD, QE,

BP3, BP2, BP1, BP0) become read-

only, and a WRSR instruction will be ignored. If the SRWD is set to “1” and

WP# is pulled high (VIH), the Status Register can be changed by a WRSR instruction.

QE bit: The Quad Enable (QE) is a non-volatile bit in the Status Register that allows quad operation. When the QE

bit is set to “0”, the pin WP# and HOLD#/RESET# are enabled. When the QE bit is set to “1”, the IO2 and IO3 pins

are enabled.

WARNING: The QE bit must be set

to “0” if WP# or HOLD#/RESET# pin (or ball) is tied directly to the power supply.

IS25LE512M-RHLA3:P-TY 데이터시트(PDF) 25 Page - Integrated Silicon Solution, Inc