IS25LE512M-RHLA3:P-TY datasheet(39/189 Pages) ISSI

39 / 189 page

IS25LE512M

IS25WE512M

Integrated Silicon Solution, Inc.- www.issi.com

Rev. A6

06/16/2025

6.7 ECC REGISTER

Related Commands: Read ECC Register (RDECC B3h) (1), Write ECC Register (WRECC B5h), Clear ECC Register

(CLECC, B6h).

Note:

1. 512Mb is an MCP of two 256Mb die, so the ECC register data after RDECC command is from one die

(previously selected die), and additional dummy read from another die (to select another die) + RDECC

command is required to get ECC register data from another die .

Table 6.26 ECC Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

IPA_ECCB

ECCCOUNTER

ECCEVENT

ECCONOFF

Default

Table 6.27 ECC Register Bit Definition (per die)

Bit

Name

Definition

Read-

/Write

Type

ECCONOFF

ECC ON/OFF bit:

"0" indicates ECC is ON (default)

"1" indicates ECC is OFF

R/W

Volatile

ECCEVENT

ECC Event bit:

"0" indicates NO ECC correction event (default)

"1" indicates YES ECC correction event

Volatile

5:2

ECCCOUNTER

Store cumulative ECC correction occurrence.

Max. 15 ECC correction occurrence can be stored, and stays 15

after further occurrence.

“0000” is the default value.

Volatile

IPA_ECCB

Incremental Programming Attempt within ECC boundary bit:

“0” indicates NO IPA within ECC Boundary (default)

“1” indicates YES IPA with ECC Boundary.

Incremental Programming within ECC boundary is not allowed, and

automatically ignored when ECC is ON.

Volatile

Reserved

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