17

Integrated

Circuit

Systems, Inc.

ICS932S422C

1412A—12/10/07

PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.

When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is

PD, Power Down

D

PU

P

C#

U

P

CC

R

S#

C

R

SI

C

P

/

F

I

C

PB

S

UF

E

Re

t

o

N

1l

a

m

r

o

Nl

a

m

r

o

Nl

a

m

r

o

Nl

a

m

r

o

Nz

H

M

3

3z

H

M

8

4z

H

M

8

1

3

.

4

11

0r

o

2

*

f

e

r

I

t

a

o

l

F

t

a

o

l

F2

*

f

e

r

I

t

a

o

l

F

r

o

t

a

o

l

Fw

o

Lw

o

Lw

o

L1

Notes:

1. Refer to SMBus Byte 4 for additional information.

PD should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be

held low on their next high to low transition.

All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register

determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.

When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x

Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.

See SMBus Byte 4 for additional information.

PD Assertion

CPU, SRC and PCI Divider Ratios

Div(3:0)

Divider

00000

2

10001

3

20010

5

30011

15

40100

4

50101

6

60110

10

70111

30

81000

8

91001

12

10

1010

20

11

1011

60

12

1100

16

13

1101

24

14

1110

40

15

1111

120

REF Drive Strength Functionality

Byte6,

bit 4

Byte 10,

bit 1

Byte 10,

bit 0

REF1

REF0

0X

X

1x

1x

10

0

1x

1x

10

1

1x

2x

11

0

2x

1x

11

1

2x

2x

PD

CPU, 133MHz

CPU#, 133MHz

SRC, 100MHz

SRC#, 100MHz

USB, 48MHz

PCI, 33MHz

REF, 14.31818