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FC106 데이터시트(PDF) 22 Page - STMicroelectronics |
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FC106 데이터시트(HTML) 22 Page - STMicroelectronics |
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22 / 32 page ![]() FC106 Revision 1.2 22/32 September 98 Figure 6.3 Receive clock latency Table 6.3 Receive clock latency characteristics Parameter Description Min Typ Max Units TRLA Data Reception Latency: Serial (first bit at receiver) to 10-bit parallel output sampled by RBC[0,1]. --5 RBC cycles +4 ns ns RBC[1] RBC[0] bit 0 of serial data 1 TX+ RX[0:9] TRLA DATA 1 |
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