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ICS002AI41L 데이터시트(PDF) 3 Page - Integrated Device Technology |
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ICS002AI41L 데이터시트(HTML) 3 Page - Integrated Device Technology |
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3 / 23 page ![]() ICS843002I-41 700MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR 3 ICS843002AKI-41 REV. A OCTOBER 25, 2007 Table 1. Pin Descriptions NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. Number Name Type Description 1, 2 LF1, LF0 Analog Input/Output Loop filter connection node pins. 3 ISET Analog Input/Output Charge pump current setting pin. 4VCC Power Core power supply pin. 5 CLK0 Input Pulldown Non-inverting differential clock input. 6nCLK0 Input Pullup Pulldown Inverting differential clock input. VCC/2 bias voltage when left floating. 7 CLK_SEL Input Pulldown Input clock select. LVCMOS/LVTTL interface levels. See Table 3A. 8 QA_SEL2 Input Pulldown Output divider control for QA/nQA LVPECL outputs. LVCMOS/LVTTL interface levels.See Table 3C. 9, 10 QA_SEL1, QA_SEL0 Input Pullup Output divider control for QA/nQA LVPECL outputs. LVCMOS/LVTTL interface levels.See Table 3C. 11 QB_SEL2 Input Pulldown Output divider control for QB/nQB LVPECL outputs. LVCMOS/LVTTL interface levels.See Table 3C. 12, 13 QB_SEL1, QB_SEL0 Input Pullup Output divider control for QB/nQB LVPECL outputs. LVCMOS/LVTTL interface levels.See Table 3C. 14 VCCA Power Analog supply pin. 15, 16 QA, nQA Output Differential clock output pair. LVPECL interface levels. 17, 27 VEE Power Negative supply pins. 18, 19 QB, nQB Output Differential clock output pair. LVPECL interface levels. 20 VCCO_LVPECL Power Output supply pin for LVPECL outputs. 21 VCCO_LVCMOS Power Output supply pin for LVCMOS/LVTTL outputs. 22 nc Unused No connect. 23 LOR1 Output Alarm output, loss of reference for CLK1/nCLK1. LVCMOS/LVTTL interface levels. 24 LOR0 Output Alarm output, loss of reference for CLK0/nCLK0. LVCMOS/LVTTL interface levels. 25 nCLK1 Input Pullup Pulldown Inverting differential clock input. VCC/2 bias voltage when left floating. 26 CLK1 Input Pulldown Non-inverting differential clock input. 28, 29, 30 R_SEL0, R_SEL1, R_SEL2 Input Pulldown Input divider selection. LVCMOS/LVTTL interface levels. See Table 3B. 31, 32 XTAL_OUT, XTAL_IN Input Crystal oscillator interface. The XTAL_IN is the input. XTAL_OUT is the output. |
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