전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

ICS002AI41L 데이터시트(PDF) 12 Page - Integrated Device Technology

부품명 ICS002AI41L
상세설명  700MHZ, FEMTOCLOCKTM VCXO BASED SONET/SDH JITTER ATTENUATOR
PDF  23 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  IDT [Integrated Device Technology]
홈페이지  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS002AI41L 데이터시트(HTML) 12 Page - Integrated Device Technology

Back Button ICS002AI41L Datasheet HTML 8Page - Integrated Device Technology ICS002AI41L Datasheet HTML 9Page - Integrated Device Technology ICS002AI41L Datasheet HTML 10Page - Integrated Device Technology ICS002AI41L Datasheet HTML 11Page - Integrated Device Technology ICS002AI41L Datasheet HTML 12Page - Integrated Device Technology ICS002AI41L Datasheet HTML 13Page - Integrated Device Technology ICS002AI41L Datasheet HTML 14Page - Integrated Device Technology ICS002AI41L Datasheet HTML 15Page - Integrated Device Technology ICS002AI41L Datasheet HTML 16Page - Integrated Device Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 12 / 23 page
background image
ICS843002I-41
700MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
12
ICS843002AKI-41 REV. A OCTOBER 25, 2007
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
R1
50
R2
50
1.8V
Zo = 50
Ω
Zo = 50
Ω
CLK
nCLK
3.3V
LVHSTL
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
R3
125
R4
125
R1
84
R2
84
3.3V
Zo = 50
Ω
Zo = 50
Ω
CLK
nCLK
3.3V
3.3V
LVPECL
HiPerClockS
Input
HCSL
*R3
33
*R4
33
CLK
nCLK
2.5V
3.3V
Zo = 50
Ω
Zo = 50
Ω
HiPerClockS
Input
R1
50
R2
50
*Optional – R3 and R4 can be 0
Ω
CLK
nCLK
HiPerClockS
Input
LVPECL
3.3V
Zo = 50
Ω
Zo = 50
Ω
3.3V
R1
50
R2
50
R2
50
3.3V
R1
100
LVDS
CLK
nCLK
3.3V
Receiver
Zo = 50
Ω
Zo = 50
Ω
CLK
nCLK
HiPerClockS
SSTL
2.5V
Zo = 60
Ω
Zo = 60
Ω
2.5V
3.3V
R1
120
R2
120
R3
120
R4
120



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com