condition. This bit is high if the temperature is greater than or equal to THIGH. This bit is low if the temperature is

less than TLOW. See Figure 7-5 for details of this sequence.

If multiple devices on the bus respond to the SMBus Alert command, arbitration during the slave address portion

of the SMBus Alert command determine which device clears its ALERT status. If the TMP75 or TMP175 wins

the arbitration, its ALERT pin becomes inactive at the completion of the SMBus Alert command. If the TMP75 or

TMP175 loses the arbitration, its ALERT pin remains active.

7.3.2.6 General Call

The TMP175 and TMP75 respond to a two-wire general call address (0000000) if the eighth bit is 0. The device

acknowledges the general call address and responds to commands in the second byte. If the second byte is

00000100, the TMP175 and TMP75 latch the status of their address pins, but do not reset. If the second byte is

00000110, the TMP175 and TMP75 latch the status of their address pins and reset their internal registers to their

power-up values.

7.3.2.7 High-Speed Mode

In order for the two-wire bus to operate at frequencies above 400 kHz, the master device must issue an

Hs-mode master code (00001XXX) as the first byte after a START condition to switch the bus to high-speed

operation. The TMP175 and TMP75 devices do not acknowledge this byte, but do switch their input filters on

SDA and SCL and their output filters on SDA to operate in Hs-mode, allowing transfers at up to 2 MHz. After

the Hs-mode master code is issued, the master transmits a two-wire slave address to initiate a data transfer

operation. The bus continues to operate in Hs-mode until a STOP condition occurs on the bus. Upon receiving

the STOP condition, the TMP175 and TMP75 switch the input and output filter back to fast-mode operation.

7.3.2.8 Time-out Function

The TMP175 resets the serial interface if either SCL or SDA is held low for 54 ms (typical) between a START

and STOP condition. The TMP175 releases the bus if it is pulled low and waits for a START condition. To

avoid activating the time-out function, a communication speed of at least 1 kHz must be maintained for the SCL

operating frequency.

7.3.3 Timing Diagrams

The TMP175 and TMP75 devices are two-wire, SMBus, and I2C interface-compatible. Figure 7-1 to Figure

7-5 describe the various operations on the TMP175. The following list provides bus definitions. Parameters for

Figure 7-1 are defined in the I2C Interface Timing.

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low when the SCL line is high defines a

START condition. Each data transfer is initiated with a START condition.

Stop Data Transfer: A change in the state of the SDA line from low to high when the SCL line is high defines a

STOP condition. Each data transfer is terminated with a repeated START or STOP condition.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the master device. The receiver acknowledges the transfer of data.

Acknowledge: Each receiving device, when addressed, is obliged to generate an Acknowledge bit. A device

that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA

line is stable low during the high period of the Acknowledge clock pulse. Setup and hold times must be taken into

account. On a master receive, the termination of the data transfer can be signaled by the master generating a

Not-Acknowledge on the last byte that is transmitted by the slave.

TMP175, TMP75

SBOS288M – JANUARY 2004 – REVISED DECEMBER 2020

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