9.2.1 Design Requirements

The purpose of this precision design is to implement an optimized single channel sample-and-hold circuit using

a precision 1:1 (SPST) CMOS switch. The sample-and-hold circuit needs to be capable of supporting high

accuracy with minimized pedestal error and fast settling time.

9.2.2 Detailed Design Procedure

The TMUX1101 or TMUX1102 switch is used in conjunction with the voltage holding capacitors (CH) to

implement the sample-and-hold circuit. The basic operation is:

1. When the switch is closed, it samples the input voltage and charges the holding capacitors (CH) to the input

voltage values.

2. When the switch is open, the holding capacitors (CH) holds its previous value, maintaining stable voltage at

the amplifier output (VOUT).

Due to switch and capacitor leakage current, as well as amplifier bias current, the voltage on the hold capacitors

droops with time. The TMUX1101 and TMUX1102 minimize the droops due to its ultra-low leakage performance.

At 25°C, the TMUX1101 and TMUX1102 have extremely low leakage current of 3pA typical.

Refer to Sample and Hold Glitch Reduction for Precision Outputs Reference Design for more information on

sample-and-hold circuits.

9.2.3 Application Curve

TMUX1101 and TMUX1102 have excellent charge injection performance and ultra-low leakage current, making

them excellent choices to minimize sampling error for the sample-and-hold application. The charge injection and

leakage performance are shown in Figure 9-2 and Figure 9-3 respectively.

VS - Source Voltage (V)

0

1

2

3

4

5

-20

-15

-10

-5

0

5

10

15

20

D011

VDD = 3.3 V

VDD = 5 V

TA = –40°C to +125°C

Figure 9-2. Charge Injection vs Source Voltage

VS or VD - Source or Drain Voltage (V)

0

1

2

3

4

5

-80

-60

-40

-20

0

20

40

60

80

D006

VDD = 5V

Figure 9-3. On-Leakage vs Source or Drain Voltage

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TMUX1101, TMUX1102

SCDS410D – MARCH 2019 – REVISED FEBRUARY 2024

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