IS43TR16640C datasheet(21/89 Pages) ISSI

21 / 89 page

IS43/46TR16640C, IS43/46TR16640CL

IS43/46TR81280C, IS43/46TR81280CL

Integrated Silicon Solution, Inc. – www.issi.com –

Rev. E

12/27/2024

2.4.5 DLL on/off switching procedure

DDR3 DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until A0 bit

set back to “0”.

2.4.5.1 DLL “on” to DLL “off” Procedure

To switch from DLL “on” to DLL “off” requires te frequency to be changed during Self-Refresh outlined in the following

procedure:

1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT,

must be in high impedance state before MRS to MR1 to disable the DLL).

2. Set MR1 Bit A0 to “1” to disable the DLL.

3. Wait tMOD.

4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.

5. Change frequency, in guidance with “Input Clock Frequency Change” section.

6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.

7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings from

any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when Self

Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from any

MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh mode was

entered, ODT signal can be registered LOW or HIGH.

8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may be

necessary. A ZQCL command may also be issued after tXS).

9. Wait for tMOD, and then DRAM is ready for next command.

2.4.5.2 DLL “off” to DLL “on” Procedure

To switch from DLL “off” to DLL “on” (with required frequency change) during Self-Refresh:

1. Starting from Idle state (All banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT)

must be in high impedance state before Self-Refresh mode is entered.)

2. Enter Self Refresh Mode, wait until tCKSRE satisfied.

3. Change frequency, in guidance with "Input clock frequency change".

4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.

5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from

subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers

when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until tDLLK timings from

subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self

Refresh mode was entered, ODT signal can be registered LOW or HIGH.

6. Wait tXS, then set MR1 bit A0 to “0” to enable the DLL.

7. Wait tMRD, then set MR0 bit A8 to “1” to start DLL Reset.

8. Wait tMRD, then set Mode Registers with appropriate values (especially an update of CL, CWL and WR may be

necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued during

or after tDLLK.)

9. Wait for tMOD, then DRAM is ready for next command (Remember to wait tDLLK after DLL Reset before applying

command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.

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