SHIFT RIGHT/SHIFT LEFT WITH PARALLEL INPUTS

A ”High” (”Low”) on the Shift Left/Shift Right input

allows serial data on the Shift Left Input (Shift Right

Input) to enter the register on the positive transition

of the clock signal. A ”high” on the ”A” Enable Input

disables the ”A” parallel data lines on Reg. 1 and 2

and enables the ”A” data lines on registers 3 and 4

and allows parallel data into registers 1 and 2. Other

logic schemes may be used in place of registers 3

and 4 for parallel loading. When parallel inputs are

not used Reg. 3 and 4 and associated logic are not

required.

* Shift Left input must be disabled during parallel

entry.

N-STAGE REGISTER WITH FIXED SERIAL OUTPUT LINE

TYPICAL APPLICATIONS (continued)

HCC/HCF4034B

10/16