TUSB542 datasheet(7/29 Pages) TI2

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5.9 Timing Requirements

MIN

NOM

MAX

UNIT

tIDLEEntry

Delay from U0 to electrical idle.

See Figure 5-2

tIDLEExit_U1

U1 exit time: break in electrical idle to the

transmission of LFPS

See Figure 5-2

tIDLEExit_U2U3

U2/U3 exit time: break in electrical idle to

transmission of LFPS

From the time when the far end

terminations detected for both ports

µs

tIDLEExit_DISC

U2/U3 exit time: break in electrical idle to

transmission of LFPS

From the time when the far end

terminations detected for both ports

µs

tDIFF-DLY

Differential propagation delay.

See Figure 5-1

225

tPWRUPACTIVE

Time when VCC reach 80% to device active

5.10 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tTX-RISE-FALL

Transmitter rise/fall time (see Figure 3)

20% to 80% of differential output. At

device pins.

tRF-MISMATCH

Transmitter rise/fall mismatch

20% to 80% of differential output. At

device pins

2.3

tDIFF_DLY

OUT

tDIFF_DLY

Figure 5-1. Propagation Delay Timing

tidleExit

IN+

Vcm

IN±

tidleEntry

VEID_TH

OUT+

Vcm

OUT±

Figure 5-2. Electrical Idle Mode Exit and Entry Delay Timing

80%

20%

Figure 5-3. Output Rise and Fall Times

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TUSB542

SLLSER3F – DECEMBER 2015 – REVISED DECEMBER 2023

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